1. Field of the Invention
The present invention relates to a correlator which is used in spread spectrum communications, and more particularly, to a correlator with a reduced amount of consumed power (hereinafter referred to as "consumed power") by reducing circuit scale. Still more particularly, the present invention relates to a signal extraction circuit for directly drawing out phase information from an input signal which expresses two values ("1", "0") of code data by each phase of a plurality of cycles and a correlator of spread spectrum communications utilizing circuit.
2. Description of the Related Art
FIG. 18 is a schematic view showing waveforms of signals to be processed on transmitting side in a spread spectrum communications. FIG. 19 is a block diagram showing one example of a conventional correlator.
In spread spectrum communications, original transmitted baseband data D1 are multiplied by code data in PN (pseudo noise) code sequence (hereinafter referred to as "PN code data D2", and where, "0" of transmitted baseband data D1 is assumed to be -1), and multiplication data (transmitted baseband data D1.times.PN code data D2) is BPSK (binary phase shift keying) modulated to transmission signal D3, and is sent out to transmission path on the transmission side as shown in FIG. 18.
The PN code data D2 is "1" of transmitted baseband data D1 converted to, for example, the data of multiple bits (for example, 32 bits) of "1" and "0". "1" or "0" of this PN code data is called "chip" in spread spectrum communications. In BPSK modulation, the phase of the carrier is reversed at the leading edge and the trailing edge of PN code data D2, and "1" or "0" information of PN code data D2 is the transmission signal D3 expressed by the phase. To transmission signal D3, for example, 190 cycles are allocated per 1 chip of PN code data D2. Presently, if the signaling rate of transmitted baseband data D1 is 1 Mbps, chip rate of the PN code data D2 is 13 Mcps, chip length is 11 chips, and carrier frequency of transmission signal D3 is 2.4 GHz band.
On the receiving side, the above-mentioned transmission signal D3 is received, and using a frequency converter (not illustrated) such as down converter, etc., removing components of the carrier frequency and converted into signal corresponding to value of each chip of PN code data D2, and inputted into a correlator of a configuration as shown in FIG. 19 to demodulate and reproduce transmitted baseband data D1.
In the correlator shown in FIG. 19, numeral 1 is a signal transferring means utilizing CCD (charge coupled device), etc., where a signal having the components of the carrier frequency removed from inputted transmission signal D3 is taken in successively as data expressed by two values by clock signal .phi.1 of the frequency same as the chip rate of PN code data D2, and is outputted from each cell 1a while being transferred to each cell 1a of the signal transferring means 1. The two values are positive peak (+1) and negative peak (-1). The data (+1, -1) outputted from each cell 1a is multiplied by coefficient ("1" denoted to +1 and "0" denoted to -1) of the PN code (code corresponding to PN code data D2) previously set to each multiplier 2a.
Consequently, at the timing in which the data on the same list of coefficient of PN code data D2 are outputted from each cell 1a of the signal transferring means 1, multiplication result of each multiplier 2a becomes 1 (=+1.times.+1=-1.times.-1), and adding these by an adding means 3 causes addition output to achieve the peak value (correlation peak). For example, if chip length is 32 chips and number of cells of signal transferring means 1 is 32, the value of the correlation peak is 32.
Now, PN code data D2 corresponding to "0" of transmitted baseband data D1 is each reversed bit of PN code data D2, which corresponds to "1" of transmitted baseband data D1. Consequently, at the timing in which the same data as that of list of PN code data D2 corresponding to "0" of this transmitted baseband data D1 is taken in, multiplication result of each multiplier 2a is -1 (=+1.times.-1) and these are added at adding means 3, then peak value becomes negative. If the number of cells 1a is 32 as with the above-mentioned case, the value of the correlation peak is -32.
The correlation peak obtained from adding means 3, as described above, is identified as "1" when the correlation peak is positive and as "0" when it is negative, and restored and reproduced to the above-mentioned transmitted baseband data D1, and outputted to subsequent stage. As described above, by setting on correlator side a multiplication coefficient corresponding to PN code data D2 on the transmitting side, it is possible to take in transmitted baseband data D1 identified by relevant PN code data D2.
Data showing the correlation peak are inputted to a synchronous signal generator means 5, and clock signal generator means 4 is controlled by synchronous signal obtained in synchronous signal generator means 5, and phase of clock signal .phi.1 is controlled so as to match the phase of transmission signal D3.
By the way, as described above, because modulated transmission signal D3 has an extremely high carrier frequency, if it is inputted as it is into the correlator, clock signal .phi.1 operating the correlator must be matched to the frequency, but this may exceed the operating frequency limit of signal transferring means 1, and in addition, the number of cells 1a of signal transferring means 1 becomes enormous, resulting in extremely large power consumption.
Therefore, hitherto, as described above, transmission signal D3 has components of the carrier frequency removed first and converted to a signal correspond to PN code data by the frequency converter, and then taken in the correlator, but passing the signal to the frequency converter distorts waveforms by intermodulation, generates errors in extracting the transmitted baseband data D1 or requires a frequency converter, causing a problem of increased circuit scale.
Under these circumstances, the principal object of the present invention is to provide a signal extraction circuit which directly takes out phase information from the input signal expressing the two values of code data with the phase of a plurality of cycles and does not require a frequency converter, and a correlator that utilizes such signal extraction circuit. The other object of the present invention is to provide a correlator which does not need a frequency converter and which is designed to reduce consumed power.